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GEB Enterprise

GEB Enterprise



Videos and tutorials about JTAG Test

Using JTAG Technologies Live tools and Python language in prototype debug (4 Video, English)

The video illustrates how You can use the Jtag Tools in development phase to debug hardware parts of a board, performing manual and automatic connection and stuck tests or functional tests in Python Language.

JTAG ProVision, Professional Boundary-scan BSCAN Test and Programming

Demonstration of JTAG ProVision from JTAG Technologies. Tutorial about the application development toolsuite that make easy BSCAN test development.

An overview about JTAG/boundary scan test

The metodology and what You may do on Your boards, presented by JTAG Technologies.

Videos about PCI express and SOPC

Video on Smart SBC BOX with mini PCIe board

The video illustrates how build a compact, cheaper and performant custom equipment using a SBC and mini PCIe FPGA Board under Ms-Seven or Linux OS.


PCI Express is an opportunity to be seized (English)

PCI Express, un’opportunità da cogliere (Italiano)

The video short illustrates  the opportunity offered by mini PCI Express and Cabled PCI Express when You are building a “state of art” equipment.


5 Reasons to Put Your Processor on an FPGA (English)

The video illustrates why is Your convenience to put a softcore processor in Your FPGA design. Best performance, obsolescense avoidance, flexibility and others good reasons…

Videos about OPENCL and Parallel Computing

Using OpenCL on SOC CORTEX

The video illustrates the performance ratio on rendering between an application written in C running on ARM-CORTEX and the same application written using OPENCL and running on CycloneV Altera FPGA.


Running Mandelbrot on a FPGA accelerator using OPENCL

The video illustrates Watch how OpenCL program, targetted on Altera Fpga, accelerates the performance of the Mandelbrot algorithm, an iterative, arithmetically intensive floating-point algorithm


OPENCL Heterogeneous Programming

The Video that shows NVIDIA CUDA code written for a GPU ported on OPENCL and retargeted to an Altera StratixV FPGA