Courses and Training – GEB Enterprise

Our COURSES

VEC100E: Introduction to VHDL training

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VEC102E: Quartus Prime Foundation

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VEC110E: QSYS training, the System Integrator

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VEC107E: QUARTUS Prime, Timing Analysis

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VEC101E: Advanced VHDL Training

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VEC125E: Advanced Timing Analysis with TimeQuest

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The GEB Enterprise S.r.l. is an ATPP (Altera Technical Training Partner) and DSN (Design Service Network) certified partner of Altera, a leading company in FPGA market, and AAP certified partner of JTAG Technologies, organizes courses VHDL for FPGA VHDL design, for System On Programmable Chip (SOPC), for BSCAN DFT (Design For Test , BSCAN oriented), for JTAG test operators. The courses range from the VHDL language, with source level simulation in a vendor independent platform (Aldec Active HDL and/or ModelSim) to the coding-oriented synthesis. The methodologies of synthesis and optimization are focused on Altera Quartus II platform.

VEC222-Creating PCI Express Links Using FPGAs

The course will start with a high-level overview of the PCI Express protocol and from there you’ll learn the design flow to target the Hard IP for PCI Express blocks found in Cyclone® V, Arria® V and Stratix® V devices, particularly when using the Qsys system design tool. You’ll see how to debug and test your PCIe links, both through simulation and in-system. You’ll discover advanced device features to add more flexibility and capability to your PCI Express-based design. By the end of the training, you’ll feel comfortable getting your own device’s PCIe link up and running.

VEC221 Designing with an ARM-based SoC

This course is intended for hardware and firmware engineers and will leverage your knowledge of Qsys system design to guide you on implementing an Altera® SoC with the ARM® Cortex A9 hard processing system (HPS). This course focuses on the hardware aspects of using the processor in the SoC from the design, verification and debug hardware perspectives just as if the processor was external. Our intention is that you feel completely comfortable using the HPS in the SoC and know all of the resources at your disposal to work with the board designer, FPGA engineer, firmware engineer or software engineer to get up and running quickly.

VEC311- Parallel Computing with OpenCL

OpenCL is a standard for writing parallel programs for heterogeneous systems. In the FPGA environment, OpenCL constructs are synthesized into custom logic. This course introduces the basic concepts of parallel computing. It covers the constructs of the OpenCL standard & Altera flow that automatically converts kernel C code into hardware that interacts with the host. In hands-on labs, you’lll write programs to run on both the CPU & FPGA. Note. This hands-on workshop provides an introduction to OpenCL for FPGAs. For in-depth training on OpenCL & Altera’s OpenCL for FPGAs solution attend the “OpenCL for Altera FPGAs” class from an ATPP partner.

VEC321- Optimizing OpenCL for Altera FPGAs

This course covers the optimization techniques needed to implement a high performance OpenCL solution on an FPGA using the Altera SDK for OpenCL. We will discuss good coding design practices, ways to improve data processing efficiency, memory access efficiencies, and host side optimizations. We will also focus on Altera SDK for OpenCL specific features that can significantly improve OpenCL performance on FPGAs compared to other platforms.